Through the analysis of the parasitic characteristics of vias, we can see that seemingly simple vias in high-speed PCB designs can also bring great negative effects to circuit design. In order to reduce the adverse effects of the parasitic effects of vias, you can do as much as possible in the design:
1. Considering the cost and signal quality, choose a reasonably sized via size. For example, for a 6-10 layer memory module PCB design, 10/20 Mil (drill/pad) vias are preferred. For some high density, small size boards, 8/18 Mil can be used. hole. Under current technical conditions, it is difficult to use smaller size vias. For power or ground vias, larger sizes can be considered to reduce the impedance.
2. The two equations discussed above can be concluded that the use of a thinner PCB board facilitates the reduction of two parasitic parameters of the via hole.
3. The signal traces on the PCB should not be changed as much as possible. That is to say, do not use unnecessary vias.
4. The pins of the power supply and ground must be drilled in the nearest hole. The shorter the lead between the via and the pin, the better, because they will cause the inductance to increase. At the same time, the leads of the power supply and ground should be as thick as possible to reduce the impedance.
5. Place some grounded vias near the signal layer vias to provide the signal with the closest loop. You can even place a lot of extra ground vias on the PCB board. Of course, you need to be flexible when designing. The previously discussed via model is a case where there are pads on each layer, and sometimes we can reduce or even remove pads on some layers. Especially in the case of very high via density, it may lead to the formation of a broken channel in the copper layer, solving this problem. In addition to moving the location of the via, we can also consider the via in the copper layer. The pad size is reduced